library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity imem_tb is
end imem_tb;

architecture behav of imem_tb is
    component imem
        port(
        a: in std_logic_vector(31 downto 0);
        rd: out std_logic_vector(31 downto 0)
        );
    end component;

    signal a_s, rd_s: std_logic_vector(31 downto 0);

begin
    IM0: imem port map(a_s, rd_s);

    process -- Read all the instructions
        constant TOTAL_INS: natural := 16;
        variable i: natural := 0;
        type pattern is array(natural range <>) of std_logic_vector(31 downto 0);
        constant ins: pattern :=
                      (x"20080000", x"20090001", x"200a0002", x"200b0003",
                       x"200c0004", x"200d0005", x"200e0006", x"200f0007",
                       x"ac080000", x"ac090004", x"ac0a0008", x"ac0b000c",
                       x"ac0c0010", x"ac0d0014", x"ac0e0018", x"ac0f001c");
    begin
        while i < TOTAL_INS loop
            a_s(7 downto 2) <= conv_std_logic_vector(i, 6);
            wait for 2 ns;
            assert rd_s = ins(i) report "Unexpected rd!" severity error;
            i := i+1;
        end loop;
        wait;
    end process;
end behav;
